RX634 Datasheet, PDF (56/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (31 / 34)
Address
0008 C293h
Module
Symbol
SYSTEM
0008 C296h
0008 C297h
FLASH
SYSTEM
0008 C298h
0008 C29Ah
SYSTEM
SYSTEM
0008 C29Bh SYSTEM
0008 C2A0h to SYSTEM
0008 C2BFh
000A 0A00h CEC
000A 0A02h CEC
000A 0A04h CEC
000A 0A06h CEC
000A 0A08h CEC
000A 0A0Ah CEC
000A 0A0Ch CEC
000A 0A0Eh CEC
000A 0A10h CEC
000A 0A12h CEC
000A 0A14h CEC
000A 0A16h CEC
000A 0A18h CEC
000A 0A1Ah CEC
000A 0A1Ch CEC
000A 0A1Eh CEC
000A 0A20h CEC
000A 0A22h CEC
000A 0A24h CEC
Register Name
Main Clock Oscillator Forced Oscillation
Control Register
Register
Symbol
MOFCR
Number
of Bits
8
Access
Size
8
Flash Write Erase Protection Register
FWEPROR
8
8
Voltage Monitoring Circuit Control
Register
LVCMPCR
8
8
Voltage Detection Level Select Register LVDLVLR
8
8
Voltage Monitoring 1 Circuit Control
Register 0
LVD1CR0
8
8
Voltage Monitoring 2 Circuit Control
Register 0
LVD2CR0
8
8
Deep Standby Backup Register 0 to 31 DPSBKR0 to 31
8
8
CEC Local Address Setting Register
CADR
16
16
CEC Control Register 1
CECCTL1
8
8
CEC Transmission Start Bit Width Setting STATB
Register
CEC Transmission Start Bit Low Width
Setting Register
STATL
CEC Transmission Logical 0 Low Width LGC0L
Setting Register
CEC Transmission Logical 1 Low Width LGC1L
Setting Register
CEC Transmission Data Bit Width Setting DATB
Register
CEC Reception Data Sampling Time
Setting Register
NOMT
CEC Reception Start Bit Minimum Low
Width Setting Register
STATLL
CEC Reception Start Bit Maximum Low STATLH
Width Setting Register
CEC Reception Start Bit Minimum Bit
Width Setting Register
STATBL
CEC Reception Start Bit Maximum Bit
Width Setting Register
STATBH
CEC Reception Logical 0 Minimum Low LGC0LL
Width Setting Register
CEC Reception Logical 0 Maximum Low LGC0LH
Width Setting Register
CEC Reception Logical 1 Minimum Low LGC1LL
Width Setting Register
CEC Reception Logical 1 Maximum Low LGC1LH
Width Setting Register
CEC Reception Data Bit Minimum Bit
Width Setting Register
DATBL
CEC Reception Data Bit Maximum Bit
Width Setting Register
DATBH
CEC Data Bit Reference Width Setting
Register
NOMP
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Number of Access Cycles
ICLK ≥
PCLK
ICLK <
PCLK
Related
Function
Remarks
4 to 5PCLKB 2 to 3 ICLK Clock
Generation
Circuit
4 to 5PCLKB 2 to 3 ICLK Flash Memory
4 to 5PCLKB 2 to 3 ICLK LVDA
4 to 5PCLKB 2 to 3 ICLK
4 to 5PCLKB 2 to 3 ICLK
4 to 5PCLKB 2 to 3 ICLK
4 to 5PCLKB 2 to 3 ICLK Low Power
Consumption
1 to 2PCLK 1 ICLK CEC
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
1 to 2PCLK 1 ICLK
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
Not available
in 5-V
packages.
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 56 of 106