RX634 Datasheet, PDF (8/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
1.3 Block Diagram
Figure 1.2 shows a block diagram.
1. Overview
CEC
RCR × 2 channels
ROM
RAM
RX CPU
MPU
Clock
generation
circuit
ICUb
DTCa
DMACA ×
4 channels
CEC:
CEC transmission/reception circuit
RCR:
Remote control signal receiver
ICUb:
Interrupt controller
DTCa:
Data transfer controller
DMACA: DMA controller
BSC:
Bus controller
WDTA: Watchdog timer
IWDTa: Independent watchdog timer
ELC:
Event link controller
CRC:
CRC (cyclic redundancy check) calculator
SCIe, SCIf: Serial communications interface
Figure 1.2
Block Diagram
E2 DataFlash
WDTA
IWDTa
ELC
CRC
SCIe × 12 channels
SCIf × 1 channel
RSPI × 2 channels
RIIC × 3 channels
TPUa × 6 channels
MTU2a × 6 channels
POE2a
PPG
TMR × 2 channels (unit 0)
TMR × 2 channels (unit 1)
CMT × 2 channels (unit 0)
CMT × 2 channels (unit 1)
12-bit A/D converter × 16 channels
10-bit D/A converter × 2 channels
DOC
CAC
BSC
External bus
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
Port D
Port E
Port F
Port H
Port J
Port K
Port L
RSPI:
RIIC:
TPUa:
MTU2a:
POE2a:
PPG:
TMR:
CMT:
DOC:
CAC:
Serial peripheral interface
I²C bus interface
16-bit timer pulse unit
Multi-function timer pulse unit 2
Port output enable 2
Programmable pulse generator
8-bit timer
Compare match timer
Data operation circuit
Clock frequency accuracy measurement circuit
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 8 of 106