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RX634 Datasheet, PDF (67/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory
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RX634 Group
5. Electrical Characteristics
5.3.1
Clock Timing
Table 5.17 BCLK Timing
Conditions 1: VCC = AVCC0 = VREFH0 = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
Ta = –40 to +85°C
Conditions 2: VCC = AVCC0 = VREFH0 = 4.0 to 5.5 V, VREFH = 4.0 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
Ta = –40 to +85°C
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
BCLK pin output cycle time
BCLK pin output high pulse width*1
BCLK pin output low pulse width*1
BCLK pin output rising time
BCLK pin output falling time
tBcyc
tCH
tCL
tCr
tCf
37
—
—
ns Figure 5.1
5
—
—
ns
5
—
—
ns
—
—
5
ns
—
—
5
ns
Note 1. When the EXTAL external clock input is used with divided by 1 to output from the BCLK pin, the above should be satisfied with
a duty cycle of 45 to 55%.
Table 5.18 Clock Timing
Conditions 1: VCC = AVCC0 = VREFH0 = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
Ta = –40 to +85°C
Conditions 2: VCC = AVCC0 = VREFH0 = 4.0 to 5.5 V, VREFH = 4.0 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
Ta = –40 to +85°C
Item
Symbol
Min. Typ.
Max.
Test
Unit Conditions
EXTAL external clock input cycle time
tEXcyc
50
—
(62.5)*1
—
ns Figure 5.2
EXTAL external clock input high pulse width
tEXH
20
—
(25)*1
—
ns
EXTAL external clock input low pulse width
tEXL
20
—
(25)*1
—
ns
EXTAL external clock rising time
EXTAL external clock falling time
EXTAL external clock input wait time*2
Main clock oscillator oscillation frequency*3
tEXr
tEXf
tEXWT
fMAIN
—
—
—
—
1
—
8
—
5
5
—
20
(16)*1
ns
ns
ms
MHz
Main clock oscillation stabilization time (crystal)
fMAINOSC
—
—
Main clock oscillation stabilization wait time (crystal)
fMAINOSCWT
—
—
LOCO clock cycle time
tLOCOCYC
6.96
8
LOCO clock cycle time
tLOCOCYC
7.27
8
LOCO clock oscillation frequency
fLOCO
106.25 125
LOCO clock oscillation frequency
fLOCO
112.5 125
LOCO clock oscillation stabilization wait time
tLOCOWT
—
—
PLL input frequency
fPLLIN
4
—
PLL circuit oscillation frequency
tLOCOWT
104
—
PLL clock oscillation stabilization PLL operation started
time
after main clock
tPLL1
—
—
PLL clock oscillation stabilization oscillation has settled
tPLLWT1
—
—
wait time
*3
*4
9.4
8.89
143.75
137.5
20
20
200
500
*5
ms Figure 5.3
ms
μs
μs Ta = 0 to +60°C
kHz
kHz Ta = 0 to +60°C
μs Figure 5.4
MHz
MHz
μs Figure 5.5
ms
PLL clock oscillation stabilization PLL operation started
tPLL2
—
—
tMAINOSC + ms Figure 5.6
time
before main clock
tPLL1
PLL clock oscillation stabilization oscillation has settled
tPLLWT2
—
—
*5
ms
wait time
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 67 of 106
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