|
RX634 Datasheet, PDF (1/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory | |||
|
Datasheet
RX634 Group
Renesas MCUs
R01DS0255EJ0100
Rev.1.00
Feb 25, 2015
54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory, 12-bit ADC,
10-bit DAC, ELC, MPC, CEC transmission/reception, remote control signal reception
Features
â 32-bit RX CPU core
ï· Max. operating frequency: 54 MHz
Capable of 90 DMIPS in operation at 54 MHz
ï· Two types of multiply-and-accumulation unit (between
memories and between registers)
ï· 32-bit multiplier (fastest instruction execution takes one
CPU clock cycle)
ï· Divider (fastest instruction execution takes two CPU clock
cycles)
ï· Fast interrupt
ï· CISC Harvard architecture with 5-stage pipeline
ï· Variable-length instructions, ultra-compact code
ï· Supports the Memory Protection Unit (MPU)
ï· On-chip debugging circuit
â Low power design and architecture
ï· Operation from a single 2.7 to 3.6 V or 4.0 to 5.5 V supply
ï· Four low power consumption modes
â On-chip main flash memory, no wait states
ï· 54-MHz operation, 18.5-ns read cycle
ï· 1 to 2 Mbytes supported
ï· User code is programmable by on-board
â On-chip data flash memory
ï· 32 Kbytes capacities
(Number of times of reprogramming: 100,000)
ï· Programming/erasing as background operations (BGOs)
â On-chip SRAM, no wait states
ï· 128-Kbyte size capacities
ï· For instructions and operands
â DMA
ï· DMAC: Incorporates four channels
ï· DTC
â ELC
ï· Module operation can be initiated by event signals without
going through interrupts.
ï· Modules can operate while the CPU is sleeping.
â Reset and supply management
ï· Power-on reset (POR)
ï· Low voltage detection (LVD) with voltage settings
â Clock functions
ï· External crystal oscillator or internal PLL for operation at 8
to 20 MHz
ï· Internal 125-kHz LOCO
ï· Dedicated 125-kHz LOCO for the IWDT
ï· Clock frequency accuracy measurement circuit (CAC)
â Independent watchdog timer
ï· 125-kHz on-chip oscillator produces a dedicated clock signal
to drive IWDT operation.
â Useful functions for IEC60730 compliance
ï· Oscillation-stoppage detection, frequency measurement,
CRC, IWDT, self-diagnostic function for the A/D converter,
etc.
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
PLQP0144KA-A 20 Ã 20 mm, 0.5-mm pitch
â Various communications interfaces
ï· SCI with many useful functions (up to 13 channels)
Asynchronous mode, clock synchronous mode, smart card
interface, simplified SPI, simplified I2C, and extended serial
mode
ï· I2C bus interface: Transfer at up to 400 kbps (three channels)
ï· RSPI for high-speed transfer (two channels)
â CEC transmission/reception function
ï· CEC signals can be transmitted/received conforming to CEC
standard 1.4
â Remote control signal reception
ï· Two units integrated
ï· Four pattern waveform matching supported
â External address space
ï· Buses for high-speed data transfer (max. operating frequency
of 27 MHz)
ï· 4 CS areas (4 Ã 16 Mbytes)
ï· Multiplexed bus or separate bus are selectable per area.
ï· 8-, or 16-bit bus space is selectable per area
â Up to 20 extended-function timers
ï· 16-bit MTU: input capture, output compare, complementary
PWM output, phase counting mode
(six channels)
ï· 16-bit TPU: input capture, output capture, phase counting
mode (six channels)
ï· 8-bit TMR (four channels)
ï· 16-bit compare-match timers (four channels)
â 12-bit A/D converter
ï· Capable of conversion within 1 μs
ï· Sample-and-hold circuits (for three channels)
ï· Three-channel synchronized sampling available
ï· Self-diagnostic function and analog input disconnection
detection assistance function
â 10-bit D/A converter: 2 channels
â Register write protection can protect values in
important registers against overwriting
â Up to 114 pins for general I/O ports
ï· Open drain, input pull-up
â MPC
ï· Multiple locations are selectable for I/O pins of peripheral
functions
â Operating temperature range
ï· ï40 to +85ï°C
Page 1 of 106
|
▷ |