RX634 Datasheet, PDF (50/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (25 / 34)
Address
0008 B126h
0008 B127h
0008 B128h
0008 B129h
0008 B12Ah
0008 B12Bh
0008 B12Ch
0008 B12Dh
Module
Symbol
ELC
ELC
ELC
ELC
ELC
ELC
ELC
ELC
0008 B300h
0008 B301h
0008 B302h
0008 B303h
0008 B304h
0008 B305h
0008 B306h
0008 B307h
0008 B308h
0008 B309h
0008 B30Ah
0008 B30Bh
0008 B30Ch
0008 B30Dh
0008 B320h
0008 B321h
0008 B322h
0008 B323h
0008 B324h
0008 B325h
0008 B326h
0008 B327h
0008 B328h
0008 B329h
0008 B32Ah
0008 B32Bh
0008 B32Ch
0008 B32Dh
0008 B32Eh
0008 B32Fh
0008 B330h
0008 B331h
0008 B332h
0008 B333h
0008 C000h
0008 C001h
0008 C002h
0008 C003h
0008 C005h
0008 C006h
0008 C007h
0008 C008h
0008 C009h
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
SCI12
PORT0
PORT1
PORT2
PORT3
PORT5
PORT6
PORT7
PORT8
PORT9
Register Name
Register
Symbol
Port Group Control Register 2
PGC2
Port Buffer Register 1
PDBF1
Port Buffer Register 2
PDBF2
Event Link Port Setting Register 0
PEL0
Event Link Port Setting Register 1
PEL1
Event Link Port Setting Register 2
PEL2
Event Link Port Setting Register 3
PEL3
Event Link Software Event Generation
Register
ELSEGR
Serial Mode Register
SMR
Bit Rate Register
BRR
Serial Control Register
SCR
Transmit Data Register
TDR
Serial Status Register
SSR
Receive Data Register
RDR
Smart Card Mode Register
SCMR
Serial Extended Mode Register
SEMR
Noise Filter Setting Register
SNFR
I²C Mode Register 1
SIMR1
I²C Mode Register 2
SIMR2
I²C Mode Register 3
SIMR3
I²C Status Register
SISR
SPI Mode Register
SPMR
Extended Serial Module Enable Register ESMER
Control Register 0
CR0
Control Register 1
CR1
Control Register 2
CR2
Control Register 3
CR3
Port Control Register
PCR
Interrupt Control Register
ICR
Status Register
STR
Status Clear Register
STCR
Control Field 0 Data Register
CF0DR
Control Field 0 Compare Enable Register CF0CR
Control Field 0 Receive Data Register
CF0RR
Primary Control Field 1 Data Register
PCF1DR
Secondary Control Field 1 Data Register SCF1DR
Control Field 1 Compare Enable Register CF1CR
Control Field 1 Receive Data Register
CF1RR
Timer Control Register
TCR
Timer Mode Register
TMR
Timer Prescaler Register
TPRE
Timer Count Register
TCNT
Port Direction Register
PDR
Port Direction Register
PDR
Port Direction Register
PDR
Port Direction Register
PDR
Port Direction Register
PDR
Port Direction Register
PDR
Port Direction Register
PDR
Port Direction Register
PDR
Port Direction Register
PDR
Number
of Bits
8
8
8
8
8
8
8
8
Access
Size
8
8
8
8
8
8
8
8
Number of Access Cycles
ICLK ≥
PCLK
ICLK <
PCLK
Related
Function
2 to 3PCLKB 2 ICLK ELC
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK SCIe, SCIf
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK I/O Ports
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
8
8
2 to 3PCLKB 2 ICLK
Remarks
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 50 of 106