RX634 Datasheet, PDF (80/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
5. Electrical Characteristics
5.3.6
Timing of On-Chip Peripheral Modules
Table 5.24 Timing of On-Chip Peripheral Modules (1)
Conditions 1: VCC = AVCC0 = VREFH0 = 2.7 to 3.6 V, VREFH = 2.7 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
T_a = –40 to +85°C
When high-drive output is selected by the drive capacity control register
Conditions 2: VCC = AVCC0 = VREFH0 = 4.0 to 5.5 V, VREFH = 4.0 V to AVCC0, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
T_a = –40 to +85°C
When high-drive output is selected by the drive capacity control register
Item
Symbol
Min.
Test
Max. Unit^*1 Conditions
I/O ports
Input data pulse width
t_PRW
1.5
MTU/TPU
Input capture input pulse width Single-edge setting t_TICW
1.5
Both-edge setting
2.5
Timer clock pulse width
Single-edge setting t_TCKWH,
1.5
Both-edge setting
t_TCKWL
2.5
—
t_Pcyc Figure 5.20
—
t_Pcyc Figure 5.21
—
—
t_Pcyc Figure 5.22
—
Phase counting
mode
2.5
—
POE
TMR
SCI
POE# input pulse width
t_POEW
1.5
Timer clock pulse width
Single-edge setting t_TMCWH,
1.5
Both-edge setting
t_TMCWL
2.5
Input clock cycle
Asynchronous
t_Scyc
4
Clock synchronous
6
—
t_Pcyc Figure 5.23
—
t_Pcyc Figure 5.24
—
—
t_Pcyc Figure 5.25
—
Input clock pulse width
t_SCKW
0.4
Input clock rise time
t_SCKr
—
Input clock fall time
t_SCKf
—
Output clock cycle
Asynchronous
t_Scyc
16
Clock synchronous
4
0.6
t_Scyc
20
ns
20
ns
—
t_Pcyc Figure 5.26
—
A/D converter
CAC
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay time
Receive data setup time
Receive data hold time
Trigger input pulse width
CACREF input pulse width
t_SCKW
0.4
0.6
t_SCKr
—
20
t_SCKf
—
20
Clock synchronous t_TXD
—
40
Clock synchronous t_RXS
40
—
Clock synchronous t_RXH
40
—
t_Pcyc ≤ t_cac*2
t_TRGW
1.5
—
t_CACREF 4.5 t_cac + 3 t_Pcyc
—
t_Pcyc > t_cac*2
5 t_cac + 6.5 t_Pcyc
—
t_Scyc
ns
ns
ns
ns
ns
t_Pcyc
ns
ns
Figure 5.27
Note 1. t_Pcyc: PCLKB cycle
Note 2. t_cac: CAC count clock source cycle
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 80 of 106