RX634 Datasheet, PDF (26/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
4. I/O Registers
4.1 I/O Register Addresses (Address Order)
Table 4.1
List of I/O Registers (Address Order) (1 / 34)
Address
0008 0000h
0008 0002h
0008 0006h
0008 0008h
0008 000Ch
0008 0010h
0008 0014h
0008 0018h
0008 0020h
0008 0026h
0008 0028h
0008 002Ah
0008 0030h
0008 0032h
0008 0034h
0008 0035h
0008 0040h
0008 0041h
0008 00A0h
0008 00A1h
0008 00A2h
0008 00A6h
0008 00C0h
0008 00C2h
0008 00E0h
0008 00E1h
0008 00E2h
0008 00E3h
0008 03FEh
Module
Symbol
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
Register Name
Register
Symbol
Mode Monitor Register
MDMONR
Mode Status Register
MDSR
System Control Register 0
SYSCR0
System Control Register 1
SYSCR1
Standby Control Register
SBYCR
Module Stop Control Register A
MSTPCRA
Module Stop Control Register B
MSTPCRB
Module Stop Control Register C
MSTPCRC
System Clock Control Register
SCKCR
System Clock Control Register 3
SCKCR3
PLL Control Register
PLLCR
PLL Control Register 2
PLLCR2
External Bus Clock Control Register
BCKCR
Main Clock Oscillator Control Register MOSCCR
Low-Speed On-Chip Oscillator Control
Register
LOCOCR
IWDT-Dedicated On-Chip Oscillator
Control Register
ILOCOCR
Oscillation Stop Detection Control
Register
OSTDCR
Oscillation Stop Detection Status Register OSTDSR
Operating Power Control Register
OPCCR
Sleep Mode Return Clock Source
Switching Register
RSTCKCR
Main Clock Oscillator Wait Control
Register
MOSCWTCR
PLL Wait Control Register
PLLWTCR
Reset Status Register 2
RSTSR2
Software Reset Register
SWRR
Voltage Monitoring 1 Circuit Control
Register 1
LVD1CR1
Voltage Monitoring 1 Circuit Status
Register
LVD1SR
Voltage Monitoring 2 Circuit Control
Register 1
LVD2CR1
Voltage Monitoring 2 Circuit Status
Register
LVD2SR
Protect Register
PRCR
0008 1300h
0008 1304h
0008 1308h
0008 130Ah
0008 1310h
0008 2000h
0008 2004h
0008 2008h
0008 200Ch
0008 2010h
0008 2013h
0008 2014h
0008 2018h
BSC
BSC
BSC
BSC
BSC
DMAC0
DMAC0
DMAC0
DMAC0
DMAC0
DMAC0
DMAC0
DMAC0
Bus Error Status Clear Register
Bus Error Monitoring Enable Register
Bus Error Status Register 1
Bus Error Status Register 2
Bus Priority Control Register
DMA Source Address Register
DMA Destination Address Register
DMA Transfer Count Register
DMA Block Transfer Count Register
DMA Transfer Mode Register
DMA Interrupt Setting Register
DMA Address Mode Register
DMA Offset Register
BERCLR
BEREN
BERSR1
BERSR2
BUSPRI
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
DMAMD
DMOFR
Number
of Bits
16
16
16
16
16
32
32
32
32
16
16
8
8
8
8
Access
Size
16
16
16
16
16
32
32
32
32
16
16
8
8
8
8
Number of Access Cycles
ICLK ≥
PCLK
ICLK <
PCLK
Related
Function
3 ICLK
3 ICLK
Operating
Modes
3 ICLK
3 ICLK
3 ICLK
3 ICLK
Low Power
Consumption
3 ICLK
3 ICLK
3 ICLK
3 ICLK
Clock
Generation
Circuit
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
Remarks
8
8
3 ICLK
8
8
3 ICLK
8
8
8
8
8
8
3 ICLK
3 ICLK
3 ICLK
Low Power
Consumption
8
8
3 ICLK
8
8
8
8
16
16
8
8
3 ICLK
3 ICLK
3 ICLK
3 ICLK
Resets
LVDA
8
8
3 ICLK
8
8
3 ICLK
8
8
3 ICLK
16
16
8
8
8
8
8
8
16
16
16
16
32
32
32
32
32
32
16
16
16
16
8
8
16
16
32
32
3 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
Register Write
Protection
Function
Buses
DMACA
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 26 of 106