RX634 Datasheet, PDF (79/106 Pages) Renesas Technology Corp – 54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory

RX634 Group
5. Electrical Characteristics
TW1
BCLK
Address cycle
Data cycle
TWn
Tend
Tn1
Th
Address
Address/
data bus
tAD
Address cycle wait (AWAIT)
tAD
A
td(AD-ALE)
th(ALE-AD)
tAD
1 cycle fixed
Address latch
(ALE)
Data read
(RD#)
CS assert wait (CSON)
Chip select
(CS3# to CS0#)
tALED
RD assert wait (RDON)
tALED
tCSD
Normal read cycle wait (CSRWAIT)
tRSD
tRSS
tSU(DB-RD)
40 ns (min)
tS(DB-RD) 0 ns (min)
D
tRDS tRDH
tRSD
tRSS
Read-access CS extension cycle
(CSROFF)
tCSD
Figure 5.18 Example of Operation in Read Access over the External Bus (Multiplexed)
BCLK
Address
Address/
data bus
Address latch
(ALE)
Data write
(WR#)
Chip select
(CS3# to CS0#)
Address cycle
TW1
Write data output wait (WDON)
tAD
A
Address cycle wait (AWAIT)
tAD
A
tAD
1 cycle fixed
t t d(BCLK-ALE)= ALED
WR assert wait (WRON)
t t d(BCLK-ALE)= ALED
tCSD
Normal write cycle wait (CSRWAIT)
Data cycle
Tend
Tn1
Th
D
tRSD
tRSS
tRSD
tRSS
Read-access CS extension cycle
(CSROFF)
tCSD
Figure 5.19 Example of Operation in Write Access over the External Bus (Multiplexed)
R01DS0255EJ0100 Rev.1.00
Feb 25, 2015
Page 79 of 106