4524 Datasheet, PDF (93/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
AND (logical AND between accumulator and memory)
Instruction D9
D0
code
0000011000
01
2
8
16
Number of
words
1
Number of Flag CY
cycles
1
–
Skip condition
–
Operation: (A) ← (A) AND (M(DP))
Grouping: Arithmetic operation
Description: Takes the AND operation between the con-
tents of register A and the contents of
M(DP), and stores the result in register A.
B a (Branch to address a)
Instruction
code
D9
D0
Number of Number of Flag CY
0
1
1
a6 a5 a4 a3 a2 a1 a0
2
1
8
+a
a
16
words
1
cycles
1
–
Skip condition
–
Operation: (PCL) ← a6 to a0
Grouping: Branch operation
Description: Branch within a page : Branches to address
a in the identical page.
Note:
Specify the branch address within the page
including this instruction.
BL p, a (Branch Long to address a in page p)
Instruction
code
D9
D0
Number of
0
0
1
1
1
p4 p3 p2 p1 p0 0
2
E
+p
p
16
words
2
2p
1 p6 p5 a6 a5 a4 a3 a2 a1 a0 _{2 +p +a} a _{16 Grouping:}
Number of Flag CY
cycles
2
–
Branch operation
Skip condition
–
Operation:
(PCH) ← p
(PCL) ← a6 to a0
Description: Branch out of a page : Branches to address
a in page p.
Note:
p is 0 to 63 for M34524M8, and p is 0 to 95
for M34524MC, and p is 0 to 127 for
M34524ED.
BLA p (Branch Long to address (D) + (A) in page p)
Instruction D9
D0
code
0000010000
01
2
1
p6 p5 p4 0
0
p3 p2 p1 p0 ₂
2
+p
p
Operation:
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
0
16
Number of
words
2
Number of Flag CY
cycles
2
–
Skip condition
–
p _{16 Grouping: Branch operation}
Description: Branch out of a page : Branches to address
(DR2 DR1 DR0 A3 A2 A1 A0)2 specified by
registers D and A in page p.
Note:
p is 0 to 63 for M34524M8, and p is 0 to 95
for M34524MC, and p is 0 to 127 for
M34524ED.
Rev.2.00 Jul 27, 2004 page 93 of 159
REJ03B0091-0200Z