4524 Datasheet, PDF (156/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS
(Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min.
Typ.
VRST
Detection voltage (Note 1) Ta = 25 °C
3.3
3.5
2.7
IRST
Operation current
at power down
VDD = 5 V
50
(Note 2)
VDD = 3 V
30
TRST
Detection time
VDD → (VRST–0.1 V) (Note 3)
0.2
Notes 1: The detected voltage (VRST) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
2: After the SVDE instruction is executed, the voltage drop detection circuit is valid at power down mode.
3: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST–0.1 V].
BASIC TIMING DIAGRAM
Machine cycle
Mi
Parameter
Pin (signal) name
Mi+1
Unit
Max.
3.7
V
4.2
100
µA
60
1.2
ms
System clock
STCK
Port D output
Port D input
D0–D9
D0–D7
Ports P0, P1, P2, P3,
P4 output
P00–P03
P10–P13
P20–P23
P30–P33
P40–P43
Ports P0, P1, P2, P3,
P4 input
P00–P03
P10–P13
P20–P23
P30–P33
P40–P43
Interrupt input
INT0, INT1
Rev.2.00 Jul 27, 2004 page 156 of 159
REJ03B0091-0200Z