4524 Datasheet, PDF (53/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
At transmit (D7–D0: transfer data)
SIN pin
At receive
SOUT pin
Serial I/O register (SI)
D7 D6 D5 D4 D3 D2 D1 D0
SOUT pin
SIN pin
Serial I/O register (SI)
* ** ** ** *
D7 D6 D5 D4 D3 D2 D1 D0
Transfer data set
* ** ** ** *
* ^{D7 D6 D5 D4 D3 D2 D1}
Transfer start
D0 _{* * * * * * *}
* * ^{D7 D6 D5 D4 D3 D2}
D1 D0 _{* * * * * *}
* ** ** ** *
Transfer complete ^{D7 D6 D5 D4 D3 D2 D1 D0}
Fig. 39 Serial I/O register state when transfer
(1) Serial I/O register SI
Serial I/O register SI is the 8-bit data transfer serial/parallel conver-
sion register. Data can be set to register SI through registers A and
B with the TSIAB instruction. The contents of register A is transmit-
ted to the low-order 4 bits of register SI, and the contents of
register B is transmitted to the high-order 4 bits of register SI.
During transmission, each bit data is transmitted LSB first from the
lowermost bit (bit 0) of register SI, and during reception, each bit
data is received LSB first to register SI starting from the topmost bit
(bit 7).
When register SI is used as a work register without using serial I/O,
do not select the SCK pin.
(3) Serial I/O start instruction (SST)
When the SST instruction is executed, the SIOF flag is cleared to
“0” and then serial I/O transmission/reception is started.
(4) Serial I/O control register J1
Register J1 controls the synchronous clock, D6/SCK, D5/SOUT and
D4/SIN pin function. Set the contents of this register through regis-
ter A with the TJ1A instruction. The TAJ1 instruction can be used to
transfer the contents of register J1 to register A.
(2) Serial I/O transmit/receive completion flag
(SIOF)
Serial I/O transmit/receive completion flag (SIOF) is set to “1” when
serial data transmit or receive operation completes. The state of
SIOF flag can be examined with the skip instruction (SNZSI). Use
the interrupt control register V2 to select the interrupt or the skip
instruction.
The SIOF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
Rev.2.00 Jul 27, 2004 page 53 of 159
REJ03B0091-0200Z