4524 Datasheet, PDF (12/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
IAP0 instruction
Register A
A0
FR00
Pull-up transistor
A0
D
OP0A instruction T Q
K00
Key-on wakeup
“L” level
detection circuit
PU00
(Note 1)
P00 (Note 2)
IAP0 instruction
Register A
A1
FR00
Pull-up transistor
A1
D
OP0A instruction T Q
K01
Key-on wakeup
“L” level
detection circuit
PU01
(Note 1)
P01 (Note 2)
IAP0 instruction
Register A
A2
FR01
Pull-up transistor
A2
D
OP0A instruction T Q
K02
Key-on wakeup
“L” level
detection circuit
PU02
(Note 1)
P02 _{(Note 2)}
IAP0 instruction
Register A
A3
FR01
Pull-up transistor
A3
D
OP0A instruction T Q
K03
Key-on wakeup
“L” level
detection circuit
PU03
(Note 1)
P03 _{(Note 2)}
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
Port block diagram (4)
Rev.2.00 Jul 27, 2004 page 12 of 159
REJ03B0091-0200Z