4524 Datasheet, PDF (113/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction
code
D9
D0
Number of Number of Flag CY
0
0
1
0
p5 p4 p3 p2 p1 p0 ₂ 0
8
+p
p
16
words
1
cycles
3
–
Skip condition
–
Operation:
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Grouping: Arithmetic operation
Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0
are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by reg-
isters A and D in page p.
The pages which can be referred as follows;
after the SBK instruction: 64 to 127
after the RBK instruction: 0 to 63
after system is released from reset or returned from power down: 0 to 63.
Note: p is 0 to 63 for M34524M8, and p is 0 to 95 for M34524MC, and p is 0 to 127 for M34524ED.
When this instruction is executed, be careful not to over the stack because 1 stage of
stack register is used.
TABPS (Transfer data to Accumulator and register B from PreScaler)
Instruction
code
D9
D0
Number of Number of Flag CY
1
0
0
1
1
1
0
1
0
1
2
2
7
5 ₁₆
words
1
cycles
1
–
Skip condition
–
Operation:
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
Grouping: Timer operation
Description: Transfers the high-order 4 bits (TPS7–
TPS4) of prescaler to register B, and
transfers the low-order 4 bits (TPS3–TPS0)
of prescaler to register A.
TABSI (Transfer data to Accumulator and register B from register SI)
Instruction
code
D9
D0
Number of
1
0
0
1
1
1
1
0
0
0
2
2
7
8 ₁₆
words
1
Number of
cycles
1
Flag CY
–
Skip condition
–
Operation:
(B) ← (SI7–SI4)
(A) ← (SI3–SI0)
Grouping: Serial I/O operation
Description: Transfers the high-order 4 bits (SI7–SI4) of
serial I/O register SI to register B, and
transfers the low-order 4 bits (SI3–SI0) of
serial I/O register SI to register A.
TAD (Transfer data to Accumulator from register D)
Instruction
code
D9
D0
Number of Number of Flag CY
0001010001
051
words
cycles
2
16
1
1
–
Skip condition
–
Operation:
(A2–A0) ← (DR2–DR0)
(A3) ← 0
Grouping: Register to register transfer
Description: Transfers the contents of register D to the
low-order 3 bits (A2–A0) of register A.
Note:
When this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
Rev.2.00 Jul 27, 2004 page 113 of 159
REJ03B0091-0200Z