4524 Datasheet, PDF (59/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
(3) LCD RAM
RAM contains areas corresponding to the liquid crystal display.
When “1” is written to this LCD RAM, the display pixel correspond-
ing to the bit is automatically displayed.
(4) LCD drive waveform
When “1” is written to a bit in the LCD RAM data, the voltage differ-
ence between common pin and segment pin which correspond to
the bit automatically becomes lVLC3l and the display pixel at the
cross section turns on.
When returning from reset, and in the RAM back-up mode, a dis-
play pixel turns off because every segment output pin and common
output pin becomes VLC3 level.
Z
1
X
12
13
14
Y
Bits ₃
2
1
0
3
2
1
0
3
2
1
0
8
SEG0 SEG0 SEG0 SEG0 SEG8 SEG8 SEG8 SEG8 SEG16 SEG16 SEG16 SEG16
9
SEG1 SEG1 SEG1 SEG1 SEG9 SEG9 SEG9 SEG9 SEG17 SEG17 SEG17 SEG17
10
SEG2 SEG2 SEG2 SEG2 SEG10 SEG10 SEG10 SEG10 SEG18 SEG18 SEG18 SEG18
11
SEG3 SEG3 SEG3 SEG3 SEG11 SEG11 SEG11 SEG11 SEG19 SEG19 SEG19 SEG19
12
SEG4 SEG4 SEG4 SEG4 SEG12 SEG12 SEG12 SEG12
13
SEG5 SEG5 SEG5 SEG5 SEG13 SEG13 SEG13 SEG13
14
SEG6 SEG6 SEG6 SEG6 SEG14 SEG14 SEG14 SEG14
15
SEG7 SEG7 SEG7 SEG7 SEG15 SEG15 SEG15 SEG15
COM COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
Note: The area marked “
” is not the LCD display RAM.
Fig. 44 LCD RAM map
Table 18 LCD control registers
LCD control register L1
Internal dividing resistor for LCD power
L13
supply selection bit (Note 2)
L12
LCD control bit
L11
LCD duty and bias selection bits
L10
at reset : 00002
0
2r ✕ 3, 2r ✕ 2
1
r ✕ 3, r ✕ 2
0
Off
1
On
L11 L10
Duty
00
01
1/2
10
1/3
11
1/4
at power down : state retained
R/W
TAL1/TL1A
Bias
Not available
1/2
1/3
1/3
LCD control register L2
at reset : 11112
at power down : state retained
L23 VLC3/SEG0 pin function switch bit (Note 3)
0
SEG0
1
VLC3
L22 VLC2/SEG1 pin function switch bit (Note 4)
0
SEG1
1
VLC2
L21 VLC1/SEG2 pin function switch bit (Note 4)
0
SEG2
1
VLC1
L20
Internal dividing resistor for LCD power
supply control bit
0
Internal dividing resistor valid
1
Internal dividing resistor invalid
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias.
3: VLC3 is connected to VDD internally when SEG0 pin is selected.
4: Use internal dividing resistor when SEG1 and SEG2 pins are selected.
W
TL2A
Rev.2.00 Jul 27, 2004 page 59 of 159
REJ03B0091-0200Z