4524 Datasheet, PDF (112/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB3 (Transfer data to Accumulator and register B from timer 3)
Instruction
code
D9
D0
Number of
1
0
0
1
1
1
0
0
1
0
2
2
7
2 ₁₆
words
1
Number of
cycles
1
Flag CY
–
Skip condition
–
Operation:
(B) ← (T37–T34)
(A) ← (T33–T30)
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T37–T34) of
timer 3 to register B.
Transfers the low-order 4 bits (T33–T30) of
timer 3 to register A.
TAB4 (Transfer data to Accumulator and register B from timer 4)
Instruction
code
D9
D0
Number of
1
0
0
1
1
1
0
0
1
1
2
2
7
3 ₁₆
words
1
Number of
cycles
1
Flag CY
–
Skip condition
–
Operation:
(B) ← (T47–T44)
(A) ← (T43–T40)
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T47–T44) of
timer 4 to register B.
Transfers the low-order 4 bits (T43–T40) of
timer 4 to register A.
TABAD (Transfer data to Accumulator and register B from register AD)
Instruction
code
D9
D0
Number of
1001111001
279
2
16
words
1
Number of
cycles
1
Flag CY
–
Skip condition
–
Operation:
In A/D conversion mode (Q13 = 0),
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
In comparator mode (Q13 = 1),
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
(Q13 : bit 3 of A/D control register Q1)
Grouping:
Description:
A/D conversion operation
In the A/D conversion mode (Q13 = 0), trans-
fers the high-order 4 bits (AD9–AD6) of
register AD to register B, and the middle-or-
der 4 bits (AD5–AD2) of register AD to
register A. In the comparator mode (Q13 = 1),
transfers the middle-order 4 bits (AD7–AD4)
of register AD to register B, and the low-order
4 bits (AD3–AD0) of register AD to register A.
TABE (Transfer data to Accumulator and register B from register E)
Instruction
code
D9
D0
Number of Number of Flag CY
0000101010
02A
words
cycles
2
16
1
1
–
Skip condition
–
Operation:
(B) ← (E7–E4)
(A) ← (E3–E0)
Grouping: Register to register transfer
Description: Transfers the high-order 4 bits (E7–E4) of
register E to register B, and low-order 4 bits
of register E to register A.
Rev.2.00 Jul 27, 2004 page 112 of 159
REJ03B0091-0200Z