4524 Datasheet, PDF (13/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
IAP1 instruction
Register A
A0
FR02
Pull-up transistor
A0
D
OP1A instuction T Q
K10
Key-on wakeup
“L” level
detection circuit
IAP1 instruction
Register A
A1
FR02
Pull-up transistor
A1
D
OP1A instuction _{T Q}
K11
Key-on wakeup
“L” level
detection circuit
IAP1 instruction
Register A
A2
FR03
Pull-up transistor
A2
D
OP1A instuction _{T Q}
K12
Key-on wakeup
“L” level
detection circuit
IAP1 instruction
Register A
A3
FR03
Pull-up transistor
A3
D
OP1A instuction _{T Q}
K13
Key-on wakeup
“L” level
detection circuit
PU10
(Note 1)
P10 (Note 2)
PU11
(Note 1)
P11 (Note 2)
PU12
(Note 1)
P12 (Note 2)
PU13
(Note 1)
P13 ^{(Note 2)}
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
Port block diagram (5)
Rev.2.00 Jul 27, 2004 page 13 of 159
REJ03B0091-0200Z