4524 Datasheet, PDF (23/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as fol-
lows (Figure 14).
• Program counter (PC)
An interrupt address is set in program counter. The address to be
executed when returning to the main routine is automatically
stored in the stack register (SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is cleared to
“0.”
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored automatically
in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is ex-
ecuted after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an in-
terrupt address.
Use the RTI instruction to return from an interrupt service routine.
Interrupt enabled by executing the EI instruction is performed after
executing 1 instruction (just after the next instruction is executed).
Accordingly, when the EI instruction is executed just before the RTI
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)
Main
routine
Interrupt
occurs
Interrupt is
enabled
Interrupt
service routine
•
•
•
•
EI
RTI
: Interrupt enabled state
: Interrupt disabled state
• Program counter (PC)
............................................................... Each interrupt address
• Stack register (SK)
..............................................T..h..e...a..d..d..r..e..s.s...o..f...m...a..i.n...r.o..u..t.i.n..e...t.o...b..e.
executed when returning
• Interrupt enable flag (INTE)
.................................................................. 0 (Interrupt disabled)
• Interrupt request flag (only the flag for the current interrupt
source) ................................................................................... 0
• Data pointer, carry flag, registers A and B, skip flag
........ Stored in the interrupt stack register (SDP) automatically
Fig. 14 Internal state when interrupt occurs
Activated Request flag Enable bit
condition (state retained)
INT0 pin interrupt
waveform input
EXF0
V 10
Enable flag
Address 0
in page 1
INT1 pin interrupt
waveform input
EXF1
V 11
Address 2
in page 1
Timer 1
underflow
T1F
V 12
Address 4
in page 1
Timer 2
underflow
T2F
V13
Timer 3
underflow
T3F
V20
Timer 5
underflow
T5F
V 21
Address 6
in page 1
Address 8
in page 1
Address A
in page 1
A/D conversion
completed
ADF
V 22
Address C
in page 1
Timer 4
underflow
Serial I/O
transmit/receive
completed
T4F
V23
SIOF
0
1
I30
INTE
Address E
in page 1
Fig. 13 Program example of interrupt processing
Fig. 15 Interrupt system diagram
Rev.2.00 Jul 27, 2004 page 23 of 159
REJ03B0091-0200Z