4524 Datasheet, PDF (22/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.
• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every inter-
rupt enable/disable. Interrupts are enabled when INTE flag is set to
“1” with the EI instruction and disabled when INTE flag is cleared to
“0” with the DI instruction. When any interrupt occurs, the INTE flag
is automatically cleared to “0,” so that other interrupts are disabled
until the EI instruction is executed.
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2
to select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and
skip instruction.
Table 5 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the cor-
responding interrupt request flag is set to “1.” Each interrupt
request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set to “1” when the activated condi-
tion is satisfied even if the interrupt is disabled by the INTE flag or
its interrupt enable bit. Once set, the interrupt request flag retains
set until it is cleared to “0” by the interrupt occurrence or the skip
instruction.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set to “1” when the inter-
rupt disable state is released, the interrupt priority level is as
follows shown in Table 3.
Table 3 Interrupt sources
Priority _{Interrupt name}
level
1 External 0 interrupt
2 External 1 interrupt
3 Timer 1 interrupt
Activated condition
Level change of
INT0 pin
Level change of
INT1 pin
Timer 1 underflow
4 Timer 2 interrupt Timer 2 underflow
5 Timer 3 interrupt Timer 3 underflow
6 Timer 5 interrupt Timer 5 underflow
7 A/D interrupt
Completion of
A/D conversion
8 Timer 4 interrupt or Timer 4 underflow
Serial I/O interrupt or completion of
(Note)
serial I/O transmit/
receive
Interrupt
address
Address 0
in page 1
Address 2
in page 1
Address 4
in page 1
Address 6
in page 1
Address 8
in page 1
Address A
in page 1
Address C
in page 1
Address E
in page 1
Note: Timer 4 interrupt or serial I/O interrupt can be selected by the timer 4,
serial I/O interrupt source selection bit (I30).
Table 4 Interrupt request flag, interrupt enable bit and skip in-
struction
Interrupt name
Interrupt Skip instruction Interrupt
request flag
nable bit
External 0 interrupt
EXF0
SNZ0
V10
External 1 interrupt
EXF1
SNZ1
V11
Timer 1 interrupt
T1F
SNZT1
V12
Timer 2 interrupt
T2F
SNZT2
V13
Timer 3 interrupt
T3F
SNZT3
V20
Timer 5 interrupt
T5F
SNZT5
V21
A/D interrupt
Timer 4 interrupt
ADF
T4F
SNZAD
V22
SNZT4
V23
Serial I/O interrupt
SIOF
SNZSI
V23
Table 5 Interrupt enable bit function
Interrupt enable bit Occurrence of interrupt
1
Enabled
0
Disabled
Skip instruction
Invalid
Valid
Rev.2.00 Jul 27, 2004 page 22 of 159
REJ03B0091-0200Z