4524 Datasheet, PDF (56/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
Table 16 Processing sequence of data transfer from master to slave
Master (transmission)
Slave (reception)
[Initial setting]
[Initial setting]
• Setting the serial I/O mode register J1 and inter- • Setting serial I/O mode register J1, and interrupt control register V2 shown in
rupt control register V2 shown in Figure 40.
Figure 40.
TJ1A and TV2A instructions
TJ1A and TV2A instructions
• Setting the port received the reception enable • Setting the port transmitted the reception enable signal (SRDY) and outputting
signal (SRDY) to the input mode.
“H” level (reception impossible).
(Port D3 is used in this example)
(Port D3 is used in this example)
SD instruction
SD instruction
* [Transmission enable state]
*[Reception enable state]
• Storing transmission data to serial I/O register SI. • The SIOF flag is cleared to “0.”
TSIAB instruction
SST instruction
• “L” level (reception possible) is output from port D3.
RD instruction
[Transmission]
[Reception]
•Check port D3 is “L” level.
SZD instruction
•Serial transfer starts.
SST instruction
•Check transmission completes.
• Check reception completes.
SNZSI instruction
SNZSI instruction
•Wait (timing when continuously transferring)
• “H” level is output from port D3.
SD instruction
[Data processing]
1-byte data is serially transferred on this process. Subsequently, data
can be transferred continuously by repeating the process from *.
When an external clock is selected as a synchronous clock, the
clock is not controlled internally. Control the clock externally be-
cause serial transmit/receive is performed as long as clock is
externally input. (Unlike an internal clock, an external clock is not
stopped when serial transfer is completed.) However, the SIOF flag
is set to “1” when the clock is counted 8 times after executing the
SST instruction. Be sure to set the initial level of the external clock
to “H.”
Rev.2.00 Jul 27, 2004 page 56 of 159
REJ03B0091-0200Z