4524 Datasheet, PDF (80/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
Clock control register MR
MR3
MR2
Operation mode selection bits
MR1 Main clock oscillation circuit control bit
MR0 System clock selection bit
at reset : 11002
at power down : state retained
MR3 MR2
Operation mode
0 0 Through mode (frequency not divided)
0 1 Frequency divided by 2 mode
1 0 Frequency divided by 4 mode
1 1 Frequency divided by 8 mode
0
Main clock oscillation enabled
1
Main clock oscillation stop
0
Main clock (f(XIN) or f(RING))
1
Sub-clock (f(XCIN))
R/W
TAMR/
TMRA
Timer control register PA
PA0 Prescaler control bit
at reset : 02
0
Stop (state initialized)
1
Operating
at power down : 02
W
TPAA
Timer control register W1
at reset : 00002
R/W
at power down : state retained
TAW1/TW1A
W13 ^{Timer 1 count auto-stop circuit selection}
bit (Note 2)
0 Timer 1 count auto-stop circuit not selected
1 Timer 1 count auto-stop circuit selected
W12 _{Timer 1 control bit}
0 Stop (state retained)
1 Operating
W11 W10
Count source
W11
0 0 Instruction clock (INSTCK)
Timer 1 count source selection bits
W10
0 1 Prescaler output (ORCLK)
1 0 Timer 5 underflow signal (T5UDF)
1 1 CNTR0 input
Timer control register W2
W23 CNTR0 output control bit
W22 Timer 2 control bit
W21
Timer 2 count source selection bits
W20
at reset : 00002
at power down : state retained
0 Timer 1 underflow signal divided by 2 output
1 Timer 2 underflow signal divided by 2 output
0 Stop (state retained)
1 Operating
W21 W20
Count source
0 0 System clock (STCK)
0 1 Prescaler output (ORCLK)
1 0 Timer 1 underflow signal (T1UDF)
1 1 PWM signal (PWMOUT)
R/W
TAW2/TW2A
Timer control register W3
at reset : 00002
at power down : state retained
W33 ^{Timer 3 count auto-stop circuit selection}
bit (Note 3)
0 Timer 3 count auto-stop circuit not selected
1 Timer 3 count auto-stop circuit selected
W32 _{Timer 3 control bit}
0 Stop (state retained)
1 Operating
W31
Timer 3 count source selection bits
W30
(Note 4)
W31 W30
Count source
0 0 PWM signal (PWMOUT)
0 1 Prescaler output (ORCLK)
1 0 Timer 2 underflow signal (T2UDF)
1 1 CNTR1 input
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”).
4: Port C output is invalid when CNTR1 input is selected for the timer 3 count source.
R/W
TAW3/TW3A
Rev.2.00 Jul 27, 2004 page 80 of 159
REJ03B0091-0200Z