4524 Datasheet, PDF (147/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
Skip condition
Datailed description
–
– In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register
B, and the middle-order 4 bits (AD5–AD2) of register AD to register A.
In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7–AD4) of register AD to register B,
and the low-order 4 bits (AD3–AD0) of register AD to register A.
(Q13: bit 3 of A/D control register Q1)
–
– Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A.
–
–
V22 = 0: (ADF) = 1
–
–
–
–
–
–
–
–
–
– In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of
comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register.
(Q13 = bit 3 of A/D control register Q1)
– Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13
= 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
(Q13 = bit 3 of A/D control register Q1)
– When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping,
clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction. (V22: bit 2 of interrupt con-
trol register V2)
– Transfers the contents of A/D control register Q1 to register A.
– Transfers the contents of register A to A/D control register Q1.
– Transfers the contents of A/D control register Q2 to register A.
– Transfers the contents of register A to A/D control register Q2.
– Transfers the contents of A/D control register Q3 to register A.
– Transfers the contents of register A to A/D control register Q3.
– No operation; Adds 1 to program counter value, and others remain unchanged.
– Puts the system in clock operating mode by executing the POF instruction after executing the EPOF instruc-
tion.
– Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction.
–
(P) = 1
(WDF1) = 1
–
– Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction.
– Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
– Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag.
Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT
instruction.
– Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
–
– Sets referring data area to pages 0 to 63 when the TABP p instruction is executed.
This instruction is valid only for the TABP p instruction.
–
– Sets referring data area to pages 64 to 127 when the TABP p instruction is executed.
This instruction is valid only for the TABP p instruction.
–
– Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode)
when VDCE pin is “H”.
Rev.2.00 Jul 27, 2004 page 147 of 159
REJ03B0091-0200Z