4524 Datasheet, PDF (82/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
Serial I/O control register J1
at reset : 00002
at power down : state retained
R/W
TAJ1/TJ1A
J13 J12
Synchronous clock
J13
0 0 Instruction clock (INSTCK) divided by 8
Serial I/O synchronous clock selection bits 0 1 Instruction clock (INSTCK) divided by 4
J12
1 0 Instruction clock (INSTCK) divided by 2
1 1 External clock (SCK input)
J11 J10
Port function
J11
0 0 D6, D5, D4 selected/SCK, SOUT, SIN not selected
Serial I/O port function selection bits
0 1 SCK, SOUT, D4 selected/D6, D5, SIN not selected
J10
1 0 SCK, D5, SIN selected/D6, SOUT, D4 not selected
1 1 SCK, SOUT, SIN selected/D6, D5, D4 not selected
A/D control register Q1
Q13 A/D operation mode selection bit
Q12
Analog input pin selection bits
Q11
Q10
at reset : 00002
A/D conversion mode
Comparator mode
Q12 Q11 Q10
0 0 0 AIN0
0 0 1 AIN1
0 1 0 AIN2
0 1 1 AIN3
1 0 0 AIN4
1 0 1 AIN5
1 1 0 AIN6
1 1 1 AIN7
at power down : state retained
R/W
TAQ1/TQ1A
Analog input pins
A/D control register Q2
Q23 P23/AIN3 pin function selection bit
Q22 P22/AIN2 pin function selection bit
Q21 P21/AIN1 pin function selection bit
Q20 P20/AIN0 pin function selection bit
at reset : 00002
0
P23
1
AIN3
0
P22
1
AIN2
0
P21
1
AIN1
0
P20
1
AIN0
at power down : state retained
R/W
TAQ2/TQ2A
A/D control register Q3
Q33 P33/AIN7 pin function selection bit
Q32 P32/AIN6 pin function selection bit
Q31 P31/AIN5 pin function selection bit
Q30 P30/AIN4 pin function selection bit
at reset : 00002
0
P33
1
AIN7
0
P32
1
AIN6
0
P31
1
AIN5
0
P30
1
AIN4
Note: “R” represents read enabled, and “W” represents write enabled.
at power down : state retained
R/W
TAQ3/TQ3A
Rev.2.00 Jul 27, 2004 page 82 of 159
REJ03B0091-0200Z