4524 Datasheet, PDF (63/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
(1) Power-on reset
Reset can be automatically performed at power on (power-on re-
set) by the built-in power-on reset circuit. When the built-in
power-on reset circuit is used, the time for the supply voltage to
rise from 0 V must be set to 100 µs or less. If the rising time ex-
ceeds 100 µs, connect a capacitor between the RESET pin and
VSS at the shortest distance, and input “L” level to RESET pin until
the value of supply voltage reaches the minimum operating volt-
age.
(Note 1)
(Note 2)
RESET pin
(Note 1)
Pull-up transistor
100 µs or less
VDD (Note 3)
Power-on reset circuit output
Internal reset signal
Power-on reset circuit
Voltage drop detection circuit
Watchdog reset signal
Internal reset signal
WEF
Reset
state
Power-on Reset released
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
3: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 49 Structure of reset pin and its peripherals,, and power-on reset operation
Table 19 Port state at reset
Name
D0–D3
D4/SIN, D5/SOUT, D6/SCK
D7/CNTR0
D8/INT0, D9/INT1
P00–P03
P10–P13
P20/AIN0–P23/AIN3
P30/AIN4–P33/AIN7
P40–P43
C/CNTR1
Function
D0–D3
D4–D6
D7
D8, D9
P00–P03
P10–P13
P20–P23
P30–P33
P40–P43
C
Notes 1: Output latch is set to “1.”
2: Output structure is N-channel open-drain.
3: Pull-up transistor is turned OFF.
State
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2)
High-impedance (Note 1)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Note 1)
High-impedance (Note 1)
High-impedance (Notes 1, 2)
“L” (VSS) level
Rev.2.00 Jul 27, 2004 page 63 of 159
REJ03B0091-0200Z