4524 Datasheet, PDF (24/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
(6) Interrupt control registers
• Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are as-
signed to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can be
used to transfer the contents of register V1 to register A.
• Interrupt control register I3
The timer 4, serial I/O interrupt source selection bit is assigned to
register I3. Set the contents of this register through register A
with the TI3A instruction. The TAI3 instruction can be used to
transfer the contents of register I3 to register A.
• Interrupt control register V2
The timer 3, timer 5, A/D, Timer 4 and serial I/O interrupt enable
bit is assigned to register V2. Set the contents of this register
through register A with the TV2A instruction. The TAV2 instruction
can be used to transfer the contents of register V2 to register A.
Table 6 Interrupt control registers
Interrupt control register V1
V13 Timer 2 interrupt enable bit
V12 Timer 1 interrupt enable bit
V11 External 1 interrupt enable bit
V10 External 0 interrupt enable bit
Interrupt control register V2
V23 ^{Timer 4, serial I/O interrupt enable bit (Note 3)}
V22 ^{A/D interrupt enable bit}
V21 ^{Timer 5 interrupt enable bit}
V20 ^{Timer 3 interrupt enable bit}
at reset : 00002
at power down : 00002
R/W
TAV1/TV1A
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
0
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
0
Interrupt disabled (SNZ1 instruction is valid)
1
Interrupt enabled (SNZ1 instruction is invalid) (Note 2)
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
at reset : 00002
at power down : 00002
R/W
TAV2/TV2A
0 Interrupt disabled (SNZT4, SNZSI instruction is valid)
1 Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 2)
0 Interrupt disabled (SNZAD instruction is valid)
1 Interrupt enabled (SNZAD instruction is invalid) (Note 2)
0 Interrupt disabled (SNZT5 instruction is valid)
1 Interrupt enabled (SNZT5 instruction is invalid) (Note 2)
0 Interrupt disabled (SNZT3 instruction is valid)
1 Interrupt enabled (SNZT3 instruction is invalid) (Note 2)
Interrupt control register I3
at reset : 02
at power down : state retained
I30
Timer 4, serial I/O interrupt source selection
0
bit
1
Timer 4 interrupt valid, serial I/O interrupt invalid
Serial I/O interrupt valid, timer 4 interrupt invalid
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
3: Select the timer 4 interrupt or serial I/O interrupt by the timer 4, serial I/O interrupt source selection bit (I30).
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt en-
able bits (V10–V13, V20–V23), and interrupt request flag are “1.”
The interrupt actually occurs 2 to 3 machine cycles after the ma-
chine cycle in which all three conditions are satisfied. The interrupt
occurs after 3 machine cycles when the interrupt conditions are
satisfied on execution of two-cycle instructions or three-cycle in-
structions. (Refer to Figure 16).
R/W
TAI3/TI3A
Rev.2.00 Jul 27, 2004 page 24 of 159
REJ03B0091-0200Z