4524 Datasheet, PDF (66/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply voltage
drops below a set value.
The voltage drop detection circuit is valid when CPU is active while
the VDCE pin is “H”.
Even after system goes into the power down mode, the voltage
drop detection circuit is also valid with the SVDE instruction.
Execution of SVDE instruction is valid only at once.
In order to release the execution of the SVDE instruction, system
reset is not required.
S
QR
EPOF instruction +POF instruction
EPOF instruction +POF2 instruction
Internal reset signal
T5F flag
Key-on wakeup signal
Q S SVDE instruction
R Internal reset signal
VDCE
–
VRST +
Voltage drop detection circuit
Reset signal
Voltage drop detection circuit
Fig. 52 Voltage drop detection reset circuit
VDD
VRST (detection
voltage)
Voltage drop detection circuit
Reset signal
RESET pin
Microcomupter starts operation after
on-chip oscillator (internal oscillator)
clock is counted 5400 to 5424 times.
Note: Detection voltage of voltage drop detection circuit does not have hysteresis.
Fig. 53 Voltage drop detection circuit operation waveform
Table 20 Voltage drop detection circuit operation state
VDCE pin
“L”
“H”
At CPU operating
Invalid
Valid
At power down
(SVDE instruction is not executed)
Invalid
Invalid
At power down
(SVDE instruction is executed)
Invalid
Valid
s Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this prod-
uct is set up lower than the minimum value of the supply voltage
of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and re-
goes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added
to the power supply pin, the following case may cause program
failure (Figure 54);
supply voltage does not fall below to VRST, and
its voltage re-goes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VRST and re-goes up after that.
VDD
Recommended
operatng condition
min.value
VRST
VDD
Recommended
operatng condition
min.value
VRST
Fig. 54 VDD and VRST
No reset
Program failure may occur.
→ Normal operation
Reset
Rev.2.00 Jul 27, 2004 page 66 of 159
REJ03B0091-0200Z