4524 Datasheet, PDF (34/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
Register B Register A
(T4HAB)
Reload register R4H (8)
(Note 4)
(Note 5)
W41
W40
0
0
XI N
ORCLK ^1/2
1
1
Reload control circuit
Timer 4 (8)
(T4R4L)
(T4AB)
W 42
“H” interval
1
expansion
TQ
0
R
(TAB4)
Reload register R4L (8)
(T4AB)
Register B Register A
(TAB4)
W43
T4F
SIOF
C/CNTR1
PWMOUT
(To timer 2 and timer 3)
(From Serial I/O)
Port C output
PWMOD
W31
W30
QD
T3UDF
W32 R T
W61
PWMOD
I30
0
Timer 4,
Serial I/O
1
interrupt
XCIN
(Note 4)
W52
0
1
ORCLK
Timer 5 (16) (Note 6)
1 - - 4 - - - - - - - -13 14 15 16
W51, W50
11
10
01
00
W62
0
(Note 4)
W 63
0
Timer LC (4)
1
1
Reload register RLC (4)
(TLCA)
(TLCA)
Register A
T5F
Timer 5
interrupt
Timer 5 underflow signal (T5UDF)
1/2
LCD clock
INSTCK
Watchdog timer (16)
1 - - - - - - - - - - - - - - - - - - - 16
(Note 7)
WRST
instruction
SQ
WDF1
R
Reset signal S Q
(Note 9)
WEF
DWDT instruction R
+
W R S T i n s tr u c t i o n( _{N o te 8 )}
DQ
WDF2
TR
Reset signal
Watchdog
reset signal
INSTCK : Instruction clock (system clock divided by 3)
ORCLK : Prescaler output (instruction clock divided by 1 to 256)
Data is set automatically from each reload
register when timer underflows
(auto-reload function).
Notes 4: Count source is stopped by clearing to “0.”
5: XIN cannot be used as count source when bit 1 (MR1) of register MR
is set to “1” and f(XIN) oscillation is stopped.
6: This timer is initialized (initial value = FFFF16) by stop of count
source (W52 = “0”).
7: Flag WDF1 is cleared to “0” and the next instruction is skipped when
the WRST instruction is executed while flag WDF1 = “1”.
The next instruction is not skipped even when the WRST instruction
is executed while flag WDF1 = “0”.
8: Flag WEF is cleared to “0” and watchdog timer reset does not occur
when the DWDT instruction and WRST instruction are executed
continuously.
9: The WEF flag is set to “1” at system reset or RAM back-up mode.
Fig. 26 Timer structure (2)
Rev.2.00 Jul 27, 2004 page 34 of 159
REJ03B0091-0200Z