4524 Datasheet, PDF (64/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
(2) Internal state at reset
Figure 50 and 51 show internal state at reset (they are the same af-
ter system is released from reset). The contents of timers, registers,
flags and RAM except shown in Figure 50 are undefined, so set the
initial value to them.
• Program counter (PC) ..............................................................................0......0......0.......0......0... 0
Address 0 in page 0 is set to program counter.
• Interrupt enable flag (INTE) .................................................................................................. 0
• Power down flag (P) ............................................................................................................. 0
• External 0 interrupt request flag (EXF0) .............................................................................. 0
• External 1 interrupt request flag (EXF1) .............................................................................. 0
• Interrupt control register V1 ..................................................................................0.......0......0... 0
• Interrupt control register V2 ..................................................................................0.......0......0... 0
• Interrupt control register I1 ...................................................................................0.......0......0... 0
• Interrupt control register I2 ...................................................................................0.......0......0... 0
• Interrupt control register I3 ................................................................................................... 0
• Timer 1 interrupt request flag (T1F) ..................................................................................... 0
• Timer 2 interrupt request flag (T2F) ..................................................................................... 0
• Timer 3 interrupt request flag (T3F) ..................................................................................... 0
• Timer 4 interrupt request flag (T4F) ..................................................................................... 0
• Timer 5 interrupt request flag (T5F) ..................................................................................... 0
• Watchdog timer flags (WDF1, WDF2) .................................................................................. 0
• Watchdog timer enable flag (WEF) ...................................................................................... 1
• Timer control register PA ...................................................................................................... 0
• Timer control register W1 .....................................................................................0.......0......0... 0
• Timer control register W2 .....................................................................................0.......0......0... 0
• Timer control register W3 .....................................................................................0.......0......0... 0
• Timer control register W4 .....................................................................................0.......0......0... 0
• Timer control register W5 .....................................................................................0.......0......0... 0
• Timer control register W6 .....................................................................................0.......0......0... 0
• Clock control register MR .....................................................................................1.......1......0... 0
• Serial I/O transmit/receive complation flag (SIOF) .............................................................. 0
• Serial I/O mode register J1 ..................................................................................0.......0......0... 0
• Serial I/O register SI ....................................................................✕......✕.......✕......✕......✕.......✕......✕... ✕
• A/D conversion completion flag (ADF) ................................................................................. 0
• A/D control register Q1 .........................................................................................0.......0......0... 0
• A/D control register Q2 .........................................................................................0.......0......0... 0
• A/D control register Q3 .........................................................................................0.......0......0... 0
• Successive approximation register AD .........................✕........✕......✕......✕.......✕......✕......✕.......✕......✕... ✕
• Comparator register .....................................................................✕......✕.......✕......✕......✕.......✕......✕... ✕
• LCD control register L1 ........................................................................................0.......0......0... 0
• LCD control register L2 ........................................................................................1.......1......1... 1
00000000
(Interrupt disabled)
(Interrupt disabled)
(Interrupt disabled)
(Prescaler stopped)
(Timer 1 stopped)
(Timer 2 stopped)
(Timer 3 stopped)
(Timer 4 stopped)
(Timer 5 stopped)
(Timer LC stopped)
(External clock selected,
serial I/O port not selected)
“✕” represents undefined.
Fig. 50 Internal state at reset
Rev.2.00 Jul 27, 2004 page 64 of 159
REJ03B0091-0200Z