4524 Datasheet, PDF (151/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
RECOMMENDED OPERATING CONDITIONS 1
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 2 to 5.5 V, unless otherwise noted)
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 2.5 to 5.5 V, unless otherwise noted)
Symbol
Parameter
Conditions
VDD
Supply voltage
(when ceramic resonator is used)
VDD
VRAM
VSS
VLC3
Supply voltage
(when RC oscillation is used)
RAM back-up voltage
Supply voltage
LCD power supply (Note 1)
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
IOH(peak)
“H” level input voltage
“H” level input voltage
“H” level input voltage
“H” level input voltage
“L” level input voltage
“L” level input voltage
“L” level input voltage
“L” level input voltage
“H” level peak output current
IOH(peak) “H” level peak output current
IOH(avg)
IOH(avg)
IOL(peak)
“H” level average output current
(Note 2)
“H” level average output current
(Note 2)
“L” level peak output current
IOL(peak) “L” level peak output current
IOL(peak) “L” level peak output current
IOL(avg)
IOL(avg)
IOL(avg)
ΣIOH(avg)
“L” level average output current
(Note 2)
“L” level average output current
(Note 2)
“L” level average output current
(Note 2)
“H” level total average current
ΣIOL(avg) “L” level total average current
Mask ROM version
f(STCK) ≤ 6 MHz
f(STCK) ≤ 4.4 MHz
f(STCK) ≤ 2.2 MHz
One Time PROM version f(STCK) ≤ 6 MHz
f(STCK) ≤ 4.4 MHz
f(STCK) ≤ 2.2 MHz
f(STCK) ≤ 4.4 MHz
at RAM back-up mode
Mask ROM version
One Time PROM version
P0, P1, P2, P3, P4, D0–D7, VDCE
XIN, XCIN
RESET
SCK, SIN, CNTR0, CNTR1, INT0, INT1
P0, P1, P2, P3, P4, D0–D7, VDCE
XIN, XCIN
RESET
SCK, SIN, CNTR0, CNTR1, INT0, INT1
P0, P1, P4, D0–D6
VDD = 5 V
SCK, SOUT
VDD = 3 V
D7, C
CNTR0, CNTR1
VDD = 5 V
VDD = 3 V
P0, P1, P4, D0–D6
VDD = 5 V
SCK, SOUT
VDD = 3 V
D7, C
VDD = 5 V
CNTR0, CNTR1
VDD = 3 V
P0, P1, P4
VDD = 5 V
VDD = 3 V
D0–D9, C, SCK, SOUT,
VDD = 5 V
CNTR0, CNTR1
VDD = 3 V
P2, P3, RESET
VDD = 5 V
VDD = 3 V
P0, P1, P4
VDD = 5 V
VDD = 3 V
D0–D9, C, SCK, SOUT,
VDD = 5 V
CNTR0, CNTR1
VDD = 3 V
P2, P3, RESET
VDD = 5 V
VDD = 3 V
P0, P1, D0–D6, SCK, SOUT
P4, D7, C, CNTR0, CNTR1
P0, P1, D0–D6, SCK, SOUT
P2, P3, P4, D7–D9, C, RESET, CNTR0, CNTR1
Notes 1: At 1/2 bias: VLC1 = VLC2 = (1/2)•VLC3
At 1/3 bias: VLC1 = (1/3)•VLC3, VLC2 = (2/3)•VLC3
2: The average output current is the average value during 100 ms.
Min.
4
2.7
2
4
2.7
2.5
2.7
1.8
2
2.5
0.8VDD
0.7VDD
0.85VDD
0.8VDD
0
0
0
0
Limits
Typ.
0
Max. ^Unit
5.5
V
5.5
5.5
5.5
5.5
5.5
5.5
V
V
V
VDD
V
VDD
VDD
V
VDD
V
VDD
V
VDD
V
0.2VDD V
0.3VDD V
0.3VDD V
0.15VDD V
–20 mA
–10
–30 mA
–15
–10 mA
–5
–20 mA
–10
24
mA
12
24
mA
12
10
mA
4
12
mA
6
15
mA
7
5
mA
2
–60 mA
–60
80
mA
80
Rev.2.00 Jul 27, 2004 page 151 of 159
REJ03B0091-0200Z