4524 Datasheet, PDF (4/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
PERFORMANCE OVERVIEW
Parameter
Function
Number of basic instructions
159
Minimum instruction execution time
0.5 µs (at 6 MHz oscillation frequency, in high-speed through mode)
Memory sizes ROM M34524M8 8192 words ✕ 10 bits
M34524MC 12288 words ✕ 10 bits
M34524ED 16384 words ✕ 10 bits
RAM
512 words ✕ 4 bits (including LCD display RAM 20 words ✕ 4 bits)
Input/Output D0–D7 I/O
ports
Eight independent I/O ports.
Input is examined by skip decision.
The output structure can be switched by software.
Ports D4, D5, D6 and D7 are also used as SIN, SOUT, SCK and CNTR0 pin.
D8, D9 Output
Two independent output ports.
Ports D8 and D9 are also used as INT0 and INT1, respectively.
P00–P03 I/O
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched
by software.
P10–P13 I/O
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched
by software.
P20–P23 I/O
4-bit I/O port; Ports P20–P23 are also used as AIN0–AIN3, respectively.
P30–P33 I/O
4-bit I/O port; Ports P30–P33 are also used as AIN4–AIN7, respectively.
P40–P43 I/O
4-bit I/O port; The output structure can be switched by software.
C
Output
1-bit output; Port C is also used as CNTR1 pin.
Timers
Timer 1
8-bit programmable timer with a reload register and has an event counter.
Timer 2
8-bit programmable timer with a reload register.
Timer 3
8-bit programmable timer with a reload register and has an event counter.
Timer 4
8-bit programmable timer with two reload registers.
Timer 5
16-bit timer, fixed dividing frequency
A/D converter
10-bit ✕ 1, 8-bit comparator is equipped.
Serial I/O
8-bit ✕ 1
LCD control Selective bias value
1/2, 1/3 bias
circuit
Selective duty value
2, 3, 4 duty
Common output
4
Segment output
20
Internal resistor for
power supply
2r ✕ 3, 2r ✕ 2, r ✕ 3, r ✕ 2 (they can be switched by software.)
Interrupt
Sources
9 (two for external, five for timer, A/D, serial I/O)
Nesting
1 level
Subroutine nesting
8 levels
Device structure
CMOS silicon gate
Package
64-pin plastic molded QFP (64P6N)
Operating temperature range
–20 °C to 85 °C
Supply
Mask ROM version
2 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.)
voltage
One Time PROM version 2.5 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.)
Power
Active mode
dissipation _{Clock operating mode}
2.8 mA (Ta=25°C, VDD = 5 V, f(XIN) = 6 MHz, f(XCIN) = 32 kHz, f(STCK) = f(XIN))
20 µA (Ta=25°C, VDD = 5 V, f(XCIN) = 32 kHz)
At RAM back-up
0.1 µA (Ta=25°C, VDD = 5 V)
Rev.2.00 Jul 27, 2004 page 4 of 159
REJ03B0091-0200Z