4524 Datasheet, PDF (39/161 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4524 Group
(7) Timer 5 (interrupt function)
Timer 5 is a 16-bit binary down counter.
Timer 5 starts counting after the following process;
➀ set count value by bits 0 and 1 of register W5, and
➁ set the bit 2 of register W5 to “1.”
Count source for timer 5 is the sub-clock input (XCIN).
Once count is started, when timer 5 underflows (the set count
value is counted), the timer 5 interrupt request flag (T5F) is set to
“1,” and count continues.
Bit 4 of timer 5 can be used as the timer LC count source for the
LCD clock generating.
When bit 2 of register W5 is cleared to “0”, timer 5 is initialized to
“FFFF16” and count is stopped.
Timer 5 can be used as the counter for clock because it can be op-
erated at clock operating mode (POF instruction execution). When
timer 5 underflow occurs at clock operating mode, system returns
from the power down state.
(8) Timer LC
Timer LC is a 4-bit binary down counter with the timer LC reload
register (RLC). Data can be set simultaneously in timer LC and the
reload register (RLC) with the TLCA instruction. Data cannot be
read from timer LC. Stop counting and then execute the TLCA in-
struction to set timer LC data.
Timer LC starts counting after the following process;
➀ set data in timer LC,
➁ select the count source with the bit 2 of register W6, and
➂ set the bit 3 of register W6 to “1.”
When a value set in reload register RLC is n, timer LC divides the
count source signal by n + 1 (n = 0 to 15).
Once count is started, when timer LC underflows (the next count
pulse is input after the contents of timer LC becomes “0”), new data
is loaded from reload register RLC, and count continues (auto-re-
load function).
Timer LC underflow signal divided by 2 can be used for the LCD
clock.
(9) Timer input/output pin
(D7/CNTR0 pin, C/CNTR1 pin)
CNTR0 pin is used to input the timer 1 count source and output the
timer 1 and timer 2 underflow signal divided by 2.
CNTR1 pin is used to input the timer 3 count source and output the
PWM signal generated by timer 4. When the PWM signal is output
from C/CNTR1 pin, set “0” to the output latch of port C.
The D7/CNTR0 pin function can be selected by bit 0 of register W6.
The selection of CNTR1 output signal can be controlled by bit 3 of
register W4.
When the CNTR0 input is selected for timer 1 count source, timer
1 counts the rising waveform of CNTR0 input.
When the CNTR1 input is selected for timer 3 count source, timer
3 counts the rising waveform of CNTR1 input. Also, when the
CNTR1 input is selected, the output of port C is invalid (high-im-
pedance state).
(10) Timer interrupt request flags
(T1F, T2F, T3F, T4F, T5F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the skip
instructions (SNZT1, SNZT2, SNZT3, SNZT4, SNZT5).
Use the interrupt control register V1, V2 to select an interrupt or a
skip instruction.
An interrupt request flag is cleared to “0” when an interrupt occurs
or when the next instruction is skipped with a skip instruction.
Rev.2.00 Jul 27, 2004 page 39 of 159
REJ03B0091-0200Z