HD6413003RF Datasheet, PDF (89/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

4.4 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a
start address from a vector table entry corresponding to a vector number from 0 to 3, which is
specified in the instruction code.
4.5 Stack Status after Exception Handling
Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP
CCR
PC
Note: In modes 1 and 2 only 20 PC bits are valid; the upper 4 bits are ignored.
Figure 4-5 Stack after Completion of Exception Handling
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