HD6413003RF Datasheet, PDF (431/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock
sources, obtained by prescaling the system clock (ø), for input to TCNT.
Bit 2
CKS2
0
1
Bit 1
CKS1
0
1
0
1
Bit 0
CKS0
0
1
0
1
0
1
0
1
Description
ø/2
ø/32
ø/64
ø/128
ø/256
ø/512
ø/2048
ø/4096
(Initial value)
12.2.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable and writable^*1 register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Bit
7
6
5
4
3
2
1
0
WRST RSTOE —
—
—
—
—
—
Initial value
0
0
1
1
1
1
1
1
Read/Write R/(W)^*2 R/W
—
—
—
—
—
—
Reserved bits
Reset output enable
Enables or disables external output of the reset signal
Watchdog timer reset
Indicates that a reset signal has been generated
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Notes: 1. RSTCSR is write-protected by a password. For details see section 12.2.4, Notes on
Register Access.
2. Only 0 can be written in bit 7, to clear the flag.
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