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HD6413003RF Datasheet, PDF (158/715 Pages) Renesas Technology Corp – Microcontroller (MCU) | |||
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Bit 4âStrobe Mode Select (CAS/WE): Selects 2CAS or 2WE mode. The setting of this bit is
valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled when the PSRAME or
DRAME bit is set to 1.
Bit 4
CAS/WE
0
1
Description
2WE mode
2CAS mode
(Initial value)
Bit 3âAddress Multiplex Mode Select (M9/M8): Selects 8-bit or 9-bit column addressing.
The setting of this bit is valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled
when the PSRAME or DRAME bit is set to 1.
Bit 3
M9/M8
0
1
Description
8-bit column address mode
9-bit column address mode
(Initial value)
Bit 2âRefresh Pin Enable (RFSHE): Enables or disables refresh signal output from the
RFSH pin. This bit is write-disabled when the PSRAME or DRAME bit is set to 1.
Bit 2
RFSHE Description
0
Refresh signal output at the RFSH pin is disabled
(the RFSH pin can be used as a generic input/output port)
1
Refresh signal output at the RFSH pin is enabled
(Initial value)
Bit 1âReserved: Read-only bit, always read as 1.
Bit 0âRefresh Cycle Enable (RCYCE): Enables or disables insertion of refresh cycles.
The setting of this bit is valid when PSRAME = 1 or DRAME = 1. When PSRAME = 0 and
DRAME = 0, refresh cycles are not inserted regardless of the setting of this bit.
Bit 0
RCYCE Description
0
Refresh cycles are disabled
1
Refresh cycles are enabled for area 3
(Initial value)
140
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