HD6413003RF Datasheet, PDF (417/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

11.3.2 Output Timing
If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when
the selected compare match event occurs. Figure 11-3 shows the timing of these operations for the
case of normal output in groups 2 and 3, triggered by compare match A.
ø
TCNT
GRA
Compare
match A signal
NDRB
PBDR
TP₈ to TP₁₅
N
N+1
N
n
m
n
m
n
Figure 11-3 Timing of Transfer of Next Data Register Contents and Output (Example)
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