HD6413003RF Datasheet, PDF (241/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

Figure 8-19 shows the timing when channel 0A is set up for I/O mode and channel 1 for burst
mode, and a transfer request for channel 0A is received while channel 1 is active.
DMAC cycle
(channel 1)
CPU
cycle
DMAC cycle
(channel 0A)
CPU
cycle
DMAC cycle
(channel 1)
T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂
ø
A ₂₃ to A ₀
RD
HWR , LWR
Figure 8-19 Timing of Multiple-Channel Operations in the Same Group
Multiple-Channel Operation in Different Groups: If transfers are requested on channels in
groups 0 and 1 simultaneously, or if a transfer in one group is requested during a transfer in the
other group, the DMAC operates as follows.
• When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it
activates the highest-priority channel at that time. If there are transfer requests for both
DMAC groups 0 and 1, a channel in group 0 is activated.
• Once a transfer starts on a channel in one group, requests to other channels are held pending
until that channel releases the bus.
• After each transfer in short address mode, and each externally-requested or cycle-steal
transfer in normal mode, the DMAC releases the bus and returns to step 1. If there is a
transfer request for a channel in the other group, that channel is activated immediately.
• After completion of a burst-mode transfer, or after transfer of one block in block transfer
mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a
group-0 channel while a group-1 channel is active, however, the group-1 channel releases the
bus after completing the transfer of the current byte or word. When the bus is released, if
there is a transfer request for a channel in the other group, the DMAC is activated
immediately.
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