HD6413003RF Datasheet, PDF (7/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

5.2 Register Descriptions...................................................................................................... 76
5.2.1 System Control Register (SYSCR)................................................................. 76
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ....................................... 77
5.2.3 IRQ Status Register (ISR) .............................................................................. 84
5.2.4 IRQ Enable Register (IER) ............................................................................. 85
5.2.5 IRQ Sense Control Register (ISCR) ............................................................... 86
5.3 Interrupt Sources............................................................................................................. 87
5.3.1 External Interrupts .......................................................................................... 87
5.3.2 Internal Interrupts ........................................................................................... 88
5.3.3 Interrupt Vector Table ..................................................................................... 88
5.4 Interrupt Operation ......................................................................................................... 91
5.4.1 Interrupt Handling Process ............................................................................. 91
5.4.2 Interrupt Sequence .......................................................................................... 96
5.4.3 Interrupt Response Time................................................................................. 97
5.5 Usage Notes .................................................................................................................... 98
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ................ 98
5.5.2 Instructions that Inhibit Interrupts .................................................................. 99
5.5.3 Interrupts during EEPMOV Instruction Execution......................................... 99
Section 6 Bus Controller............................................................................................ 101
6.1 Overview ........................................................................................................................ 101
6.1.1 Features........................................................................................................... 101
6.1.2 Block Diagram................................................................................................ 102
6.1.3 Input/Output Pins............................................................................................ 103
6.1.4 Register Configuration.................................................................................... 103
6.2 Register Descriptions...................................................................................................... 104
6.2.1 Bus Width Control Register (ABWCR) ......................................................... 104
6.2.2 Access State Control Register (ASTCR) ........................................................ 105
6.2.3 Wait Control Register (WCR)......................................................................... 106
6.2.4 Wait State Control Enable Register (WCER) ................................................. 107
6.2.5 Bus Release Control Register (BRCR)........................................................... 108
6.3 Operation ........................................................................................................................ 109
6.3.1 Area Division.................................................................................................. 109
6.3.2 Chip Select Signals ......................................................................................... 111
6.3.3 Data Bus.......................................................................................................... 112
6.3.4 Bus Control Signal Timing ............................................................................. 113
6.3.5 Wait Modes ..................................................................................................... 121
6.3.6 Interconnections with Memory (Example)..................................................... 127
6.3.7 Bus Arbiter Operation..................................................................................... 129
6.4 Usage Notes .................................................................................................................... 132
6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM ................................ 132