HD6413003RF Datasheet, PDF (634/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

TMDR—Timer Mode Register
H'62 ITU (all channels)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
—
MDF FDIR PWM4 PWM3 PWM2 PWM1 PWM0
1
0
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM mode 0
0 Channel 0 operates normally
1 Channel 0 operates in PWM mode
PWM mode 1
0 Channel 1 operates normally
1 Channel 1 operates in PWM mode
PWM mode 2
0 Channel 2 operates normally
1 Channel 2 operates in PWM mode
PWM mode 3
0 Channel 3 operates normally
1 Channel 3 operates in PWM mode
PWM mode 4
0 Channel 4 operates normally
1 Channel 4 operates in PWM mode
Flag direction
0 OVF is set to 1 in TSR2 when TCNT2 overflows or underflows
1 OVF is set to 1 in TSR2 when TCNT2 overflows
Phase counting mode flag
0 Channel 2 operates normally
1 Channel 2 operates in phase counting mode
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