HD6413003RF Datasheet, PDF (129/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

6.3.2 Chip Select Signals
For each of areas 0 to 7, the H8/3003 can output a chip select signal (CS₀ to CS₇) that goes low to
indicate when the area is selected. Figure 6-3 shows the output timing of a CSn signal.
Output of the CS_n signal is enabled or disabled in the data direction register (DDR) of the
corresponding port. A reset leaves pin CS₀ in the output state and pins CS₁ to CS₇ in the input
state. To output chip select signals CS₁ to CS₇, the corresponding DDR bits must be set to 1.
For details see section 9, I/O Ports.
When the on-chip RAM and on-chip registers are accessed, CS₇ goes low but the AS, RD, HWR,
and LWR signals remain high. The CS_n signals are decoded from the address signals. They can be
used as chip select signals for SRAM and other devices.
ø
Address
CS_n
T₁
T₂
T₃
External address in area n
Figure 6-3 CS_n Output Timing
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