HD6413003RF Datasheet, PDF (387/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

Contention between General Register Write and Compare Match: If a compare match occurs
in the T₃ state of a general register write cycle, writing takes priority and the compare match
signal is inhibited. See figure 10-64.
General register write cycle
T₁
T₂
T₃
ø
Address
GR address
Internal write signal
TCNT
N
N+1
GR
Compare match signal
N
M
General register write data
Inhibited
Figure 10-64 Contention between General Register Write and Compare Match
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