HD6413003RF Datasheet, PDF (279/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

9.8 Port A
9.8.1 Overview
Port A is an 8-bit input/output port that is also used for output (TP₇ to TP₀) from the
programmable timing pattern controller (TPC), input and output (TIOCB₂, TIOCA₂, TIOCB₁,
TIOCA₁, TIOCB₀, TIOCA₀, TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit integrated timer-
pulse unit (ITU), and output (TEND₁, TEND₀) from the DMA controller (DMAC). Port A has the
same set of pin functions in all operating modes. Figure 9-11 shows the pin configuration of
port A.
Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington transistor pair. Port A has Schmitt-trigger inputs.
Port A
Port A pins
PA ₇ (input/output)/TP₇ (output)/TIOCB₂ (input/output)
PA ₆ (input/output)/TP₆ (output)/TIOCA₂ (input/output)
PA ₅ (input/output)/TP₅ (output)/TIOCB₁ (input/output)
PA ₄ (input/output)/TP₄ (output)/TIOCA₁ (input/output)
PA ₃ (input/output)/TP₃ (output)/TIOCB₀ (input/output)/TCLKD (input)
PA ₂ (input/output)/TP₂ (output)/TIOCA₀ (input/output)/TCLKC (input)
PA ₁ (input/output)/TP₁ (output)/TEND₁ (output)/TCLKB (input)
PA ₀ (input/output)/TP₀ (output)/TEND₀ (output)/TCLKA (input)
Figure 9-11 Port A Pin Configuration
9.8.2 Register Descriptions
Table 9-13 summarizes the registers of port A.
Table 9-13 Port A Registers
Address*
Name
H'FFD1
Port A data direction register
H'FFD3
Port A data register
Note: * Lower 16 bits of the address.
Abbreviation
PADDR
PADR
R/W Initial Value
W
H'00
R/W H'00
261