HD6413003RF Datasheet, PDF (242/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

Figure 8-20 shows the timing when channel 0A is set up for I/O mode and channel 2 for burst
mode, and a transfer request for channel 0A is received while channel 2 is active.
DMAC cycle
(channel 2)
DMAC cycle
(channel 0A)
DMAC cycle (channel 2)
T₁ T₂ T_d T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂
ø
A ₂₃ to A ₀
RD
HWR , LWR
Figure 8-20 Timing of Multiple-Channel Operations in Different Groups
If cycle-steal mode is selected in both groups 0 and 1, the DMAC may activate channels in these
two groups alternately without passing the bus right to the CPU.
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