HD6413003RF Datasheet, PDF (234/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

8.4.8 DMAC Bus Cycle
Figure 8-13 shows an example of the timing of the basic DMAC bus cycle. This example shows a
word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the
DMAC gets the bus from the CPU, after one dead cycle (T_d), it reads from the source address and
writes to the destination address. During these read and write operations the bus is not released
even if there is another bus request. DMAC cycles comply with bus controller settings in the same
way as CPU cycles.
CPU cycle
DMAC cycle (word transfer)
CPU cycle
T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₃ T₁ T₂ T₃ T₁ T₂ T₁ T₂
ø
A₂₃ to A ₀
Source
address
Destination address
RD
HWR
LWR
Figure 8-13 DMA Transfer Bus Timing (Example)
Figure 8-14 shows the timing when the DMAC is activated by low input at a DREQ pin. This
example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state
access area. The DMAC continues the transfer while the DREQ pin is held low.
216