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| HD6413003RF Datasheet, PDF (237/715 Pages) Renesas Technology Corp – Microcontroller (MCU) | |||
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DREQ
CPU cycle
DMAC cycle
CPU
cycle DMAC cycle
T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2 Td T1 T2
A 23 to A0
RD
HWR , LWR
Minimum 4 states
Next sampling point
Figure 8-16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode
Figure 8-17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in
normal mode.
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