HD6413003RF Datasheet, PDF (120/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

6.1.2 Block Diagram
Figure 6-1 shows a block diagram of the bus controller.
CS₀ to CS₇
Internal
address bus
Area
decoder
ABWCR
ASTCR
WCER
Bus control
circuit
Internal signals
Bus mode control signal
Bus size control signal
Access state control signal
Wait request signal
WAIT
Wait-state
controller
WCR
Internal signals
CPU bus request signal
DMAC bus request signal
Refresh controller bus request signal
CPU bus acknowledge signal
DMAC bus acknowledge signal
Refresh controller bus acknowledge signal
BRCR
Bus arbiter
Legend
ABWCR: Bus width control register
ASTCR: Access state control register
WCER: Wait state controller enable register
WCR: Wait control register
BRCR: Bus release control register
BACK
BREQ
Figure 6-1 Block Diagram of Bus Controller
102