HD6413003RF Datasheet, PDF (19/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

Section 1 Overview
1.1 Overview
The H8/3003 is a microcontroller (MCU) that integrates system supporting functions together
with an H8/300H CPU core having an original Hitachi architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include RAM, a 16-bit integrated timer unit (ITU), a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, I/O ports, a direct memory access controller (DMAC), a refresh
controller, and other facilities. Four MCU operating modes offer a choice of data bus width and
address space size.
Table 1-1 summarizes the H8/3003 features.
Table 1-1 Features
Feature
CPU
Description
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers
(also useable as sixteen 8-bit registers or eight 32-bit registers)
High-speed operation
• Maximum clock rate: 16 MHz
• Add/subtract: 125 ns
• Multiply/divide: 875 ns
Two CPU operating modes
• Normal mode (64-kbyte address space, not available in the H8/3003)
• Advanced mode (16-Mbyte address space)
Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits)
• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
• Bit accumulator function
• Bit manipulation instructions with register-indirect specification of bit positions
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