HD6413003RF Datasheet, PDF (236/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

CPU cycle
DMAC cycle
CPU cycle
T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂
ø
A ₂₃ to A ₀
Source Destination
address address
RD
HWR, LWR
Figure 8-15 Burst DMA Bus Timing
When the DMAC is activated from a DREQ pin there is a minimum interval of four states from
when the transfer is requested until the DMAC starts operating. The DREQ pin is not sampled
during the time between the transfer request and the start of the transfer. In short address mode
and normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the
pin is next sampled at the end of one block transfer.
Figure 8-16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal
mode.
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