HD6413003RF Datasheet, PDF (126/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

6.2.5 Bus Release Control Register (BRCR)
BRCR is an 8-bit readable/writable register that enables or disables release of the bus to an
external device.
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
— BRLE
Initial value
1
1
1
1
1
1
1
0
Read/Write
—
—
—
—
—
—
—
R/W
Reserved bits
Bus release enable
Enables or disables
release of the bus to
an external device
BRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 1—Reserved: Read-only bits, always read as 1.
Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0
BRLE
0
1
Description
The bus cannot be released to an external device; BREQ and BACK
can be used as input/output pins
The bus can be released to an external device
(Initial value)
108