HD6413003RF Datasheet, PDF (559/715 Pages) Renesas Technology Corp – Microcontroller (MCU)

18.3.2 Refresh Controller Bus Timing
Refresh controller bus timing is shown as follows:
• DRAM bus timing
Figures 18-7 to 18-12 show the DRAM bus timing in each operating mode.
• PSRAM bus timing
Figures 18-13 and 18-14 show the pseudo-static RAM bus timing in each operating mode.
T₁
T₂
T₃
ø
t_AD
t_AD
A₉ to A₁
AS
CS3 (RAS)
t_RAD1
t_AS1
RD (CAS)
HWR (UW),
LWR (LW),
(read)
HWR (UW),
LWR (LW),
(write)
t_RAH
t_ASD
t_AS1
t_RAD3
t_SD
t_CAS
t_RP
t_CRP
t_ASD
t_RAC
t_AA
t_CAC
t_SD
t_WDH
RFSH
D₁₅ to D₀
(read)
D₁₅ to D₀
(write)
t_WDS3
t_RDS
t_RDH*
Note: * Stipulation from earliest CS3 and RD negate timing.
Figure 18-7 DRAM Bus Timing (Read/Write): Three-State Access
— 2WE Mode —
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