English
Language : 

HD6413003RF Datasheet, PDF (550/715 Pages) Renesas Technology Corp – Microcontroller (MCU)
Table 18-5 Refresh Controller Bus Timing
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition A Condition B Condition C
Item
RAS delay time 1
RAS delay time 2
RAS delay time 3
Symbol
tRAD1
tRAD2
tRAD3
8 MHz
Min Max
— 60
— 60
— 60
10 MHz
Min Max
— 50
— 50
— 50
16 MHz
Min Max
— 30
— 30
— 30
Unit
ns
Test
Conditions
Figure 18-7
to
Figure 18-13
Row address hold time* tRAH
25 — 20 — 15 —
RAS precharge time*
tRP
85 — 70 — 40 —
CAS to RAS precharge tCRP
time*
85 — 70 — 40 —
CAS pulse width
tCAS
110 — 85 — 40 —
RAS access time*
tRAC
— 160 — 150 — 85
Address access time
tAA
— 105 — 75 — 55
CAS access time
tCAC
— 50 — 50 — 25
Write data setup time 3 tWDS3 75 — 50 — 40 —
CAS setup time*
tCSR
20 — 15 — 15 —
Read strobe delay time tRSD
— 60 — 50 — 30
Note: At 8 MHz, the times below depend as indicated on the clock cycle time.
tRAH = 0.5 × tcyc – 38 (ns)
tCAC = 1.0 × tcyc – 75 (ns)
tRAC = 2.0 × tcyc – 90 (ns)
tCSR = 0.5 × tcyc – 43 (ns)
tRP = tCRP = 1.0 × tcyc – 40 (ns)
At 10 MHz, the times below depend as indicated on the clock cycle time.
tRAH = 0.5 × tcyc – 30 (ns)
tCAC = 1.0 × tcyc – 50 (ns)
tRAC = 2.0 × tcyc – 50 (ns)
tCSR = 0.5 × tcyc – 35 (ns)
tRP = tCRP = 1.0 × tcyc – 30 (ns)
At 16 MHz, the times below depend as indicated on the clock cycle time.
tRAH = 0.5 × tcyc – 16 (ns)
tRAC = 2.0 × tcyc – 40 (ns)
tRP = tCRP = 1.0 × tcyc – 23 (ns)
tCAC = 1.0 × tcyc – 38 (ns)
tCSR = 0.5 × tcyc – 16 (ns)
532