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| HD6413003RF Datasheet, PDF (235/715 Pages) Renesas Technology Corp – Microcontroller (MCU) | |||
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CPU cycle
DMAC cycle
CPU cycle
DMAC cycle
(last transfer cycle)
CPU cycle
T1 T2 T3 Td T1 T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2
ø
DREQ
A 23 to A 0
RD
HWR , LWR
TEND
Source Destination
address address
Source Destination
address address
Figure 8-14 Bus Timing of DMA Transfer Requested by Low DREQ Input
Figure 8-15 shows an auto-requested burst-mode transfer. This example shows a transfer of three
words from a 16-bit two-state access area to another 16-bit two-state access area.
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